In recent years, liquid crystal display devices and electroluminescence (EL) display devices are used widely as flat panel displays. In particular, active matrix display devices having each pixel provided with a switching element have become widespread because of their intrinsic advantages such as high contrast and quick response.
As the switching elements, nonlinear resistance elements and semiconductor elements are used, and among them TFTs formed on a transparent insulation substrate are used because they enable the transmission display and also realize a large-sized screen easily. Especially, TFTs having a semiconductor layer at a channel portion made of polysilicon (p—Si) can realize a display device with smaller power consumption and enabling a more quick response as compared with a device made of amorphous silicon (a—Si).
The manufacturing cost of such an active matrix display device including TFTs may be higher than that of a display device without switching elements. However, a technology for suppressing the manufacturing cost while employing TFTs also has been proposed.
For instance, an active matrix display device having a plurality of data lines connected to be one line, which is then connected to an output signal line of a data line drive circuit via the equal number of TFTs is known (see Patent Document 1, for example).
An active matrix liquid crystal display device having the configuration described in this Patent Document will be described below with reference to FIG. 14 showing an equivalent circuit thereof. In FIG. 14, reference numeral 100 denotes a liquid crystal panel, 102 denotes a gate line drive circuit and 103 denotes a data line drive circuit. The gate line drive circuit 102 outputs a gate signal having a scanning select voltage or a scanning non-select voltage to each gate line (scanning line) GL. The data line drive circuit 103 outputs to each data line DL a data signal that is a video signal corresponding to the data line DL.
Although not illustrated, the liquid crystal panel 100 includes a matrix substrate and an opposing substrate that are in parallel and opposed to each other with a space of a predetermined distance therebetween, the space being filled with liquid crystals.
In this liquid crystal panel, a plurality of parallel data lines DL1 to DLN and a plurality of parallel gate lines GL1 to GLM crossing the data lines DLs are provided on the matrix substrate, and at each of the intersections of these data lines DLs and the gate lines GLs, a pixel electrode (not illustrated) and a pixel TFT 11 are provided. The pixel electrode forms a pixel that is one unit of the display with an opposing electrode 12 (described later) and a liquid crystal capacitance 10, and the pixel TFT 11 is provided for electrically connecting the pixel electrode to the corresponding data line DL. While a gate electrode of this pixel TFT 11 is connected with the above-stated gate line GL, a source electrode thereof is connected with a data line DL and a drain electrode thereof is connected with a pixel electrode.
In this configuration, when a gate line select voltage is applied to the gate electrode from the above-stated gate line drive circuit 102 (hereinafter called a writing period), the pixel TFT 11 is in a low resistance state (ON state), and therefore an electric potential of the data signal showing a video signal applied to the data line DL is transmitted from the above-stated data line drive circuit 103 to the pixel electrode, so as to make the electric potential of the pixel electrode equal to that of the data line DL. On the other hand, when a gate line non-select voltage is applied to the gate electrode (hereinafter called a retention period), the pixel TFT 11 is in a high resistance state (OFF state), and therefore the electrode potential of the pixel electrode is retained at the electric potential applied during the writing.
On the opposing substrate, the opposing electrode 12 serving as the other electrode of the liquid crystal capacitance 10 is formed. The opposing electrode 12 is provided on the entire surface of the opposing substrate to be common to all of the pixels. An appropriate common voltage is applied to the opposing electrode 12 from the matrix substrate side via a common terminal (not illustrated) provided on the periphery of the matrix substrate.
A voltage equivalent to an electric potential difference between the pixel electrode and the opposing electrode 12 is applied to the liquid crystal capacitance 10. By regulating this voltage, the transmissivity of liquid crystals can be controlled, thus enabling the display of an image.
The distinctive configuration proposed in the above-stated Patent Document 1 resides in that one data line DL is connected with a different data line DL via a second TFT 13 (hereinafter called a gate TFT 13) that is different from the pixel TFT 11 for driving liquid crystals as stated above, and these two DLs are grouped to be connected to an output signal line D of the data line drive circuit 103.
In this drawing, a data line DL2 connected with an output signal line D1 of the data line drive circuit 103 is connected with a data line DL1 via a gate TFT 13-1, and a data line DL4 connected with an output signal line D2 is connected with a data line DL3 via a gate TFT 13-2. Since N=12 in this drawing, six data line groups each including two data lines are formed in a similar manner. The gate electrodes of these six gate TFTs 13-1 to 13-6 are connected to a gate line GLa, and the open/close of these gate electrodes is controlled by a data line select signal supplied from a data line selection circuit 130 to the gate line GLa.
In the thus configured liquid crystal display device, in order to update an applied voltage charged to a liquid crystal capacitance 10-1 present at the intersection of the data line DL1 and the gate line GL1, the gate TFT 13-1 and the pixel TFT 11-1 should be turned ON. Thereby, a voltage of a data signal supplied from the data line drive circuit 103 to the data line DL1 is applied to the pixel electrode that is one of the electrodes of the liquid crystal capacitance 10-1, whereby the applied voltage of the liquid crystal capacitance 10-1 can be updated.
Incidentally, at this time, the applied voltage charged to a liquid crystal capacitance 10-2 present at the intersection of the data line DL2 and the gate line GL1 also is varied. However, immediately after the completion of the charge to the liquid crystal capacitance 11-1, the gate TFT 13-1 may be turned OFF, and at the same time a data signal output from the output signal line D1 may be updated, whereby the liquid crystal capacitance 10-2 can be recharged with a correct voltage.
FIG. 15 illustrates waveforms of drive signals applied to the liquid crystal panel 100 at this time (vertical synchronizing signal, horizontal synchronizing signal, data signal, data line selection signal that is a control signal of a gate TFT 13 and a gate signal applied to gate lines GL1 to GLM that is a control signal of a pixel TFT 11). Note here that the pixel TFTs 11 and the gate TFTs 13 used here are turned ON with a positive voltage as in the case of a n-channel FET, and M is 8.
With this configuration, the number of output buffers within the data line drive circuit 103 can be reduced to half of the number of the data lines DLs. This leads to a cost reduction that is more than the compensation for the cost-up due to the data line selection circuit 130 added for controlling the driving of the gate TFTs 13. The data line selection circuit 130 can be integrated within the gate line drive circuit 102 easily, and therefore it does not lead to a significant cost-up. Furthermore, since the number of the output signal lines D of the data line drive circuit 103 can be reduced to half as well, the assembly cost also can be reduced.
In the configuration of FIG. 14, however, since the driving order of the grouped data lines DLs is fixed to an arrangement order of the data lines DLs that is in accordance with the scanning direction, there is a problem of a display unevenness in a stripe pattern as described below, thus degrading an image quality.
TFTs have an intrinsic parasitic capacitance (stray capacitance), and in the case of the liquid crystal display of FIG. 14, there are a capacitance C1 between source and drain and a capacitance C2 between gate and drain of a gate TFT 13. Furthermore, although not illustrated, a pixel TFT 11 also has a similar stray capacitance. Moreover, a coupling capacitance C3 is present at an intersection of a data line DL and a gate line GL, and a capacitance C4 is present between a data line DL and an opposing electrode 12. In the case of TFTs made of amorphous silicon, the ON resistance reaches a several mega Ω, and therefore even a parasitic capacitance cannot be ignored.
In particular, when the electric potential of the gate line GLa falls, there is a considerable influence of the leak of electric charge in the liquid crystal capacitance 10-1 through the capacitance C2. Furthermore, during the charging of the liquid crystal capacitance 11-2, since the pixel TFT 11-1 in the adjacent pixel also is in ON state, the electric charge may be transferred between the capacitance C4 and the liquid crystal capacitance 10-1 due to an even small factor.
In a liquid crystal display device, the transmissivity is determined by an effective value of a voltage applied to liquid crystals. Therefore, even when trying to display a solid image, a display unevenness in a vertical striped shape corresponding to one dot occurs in the image because there is a difference in voltages applied to the liquid crystal capacitances 10 between the pixels driven by an odd-numbered data line DL1, DL3, . . . (group a) and the pixels driven by an even-numbered data line DL2, DL4, . . . (group b) of two data lines DLs forming a group, and therefore a practically sufficient image quality cannot be obtained.
Such an electric potential variation in the liquid crystal capacitance 10 results from a parasitic capacitance present between a pixel electrode of each pixel and a data line DL located on the right side. If such a parasitic capacitance is present, an electric potential variation in the data line located on the right side will be conveyed to a pixel electrode in an adjacent pixel on the left side that is the other electrode of the parasitic capacitance because of the capacitive coupling, so that the charged voltage of the liquid crystal capacitance 10 of the corresponding pixel will be varied.
More specifically, a variation range of the electric potential of the liquid crystal capacitance 10 due to the electric potential variation in the adjacent data line DL will be as follows: in the case where the electric potential is varied in the data line DL by 4 V, ΔV=4×Csd/(Cpix+Csd)=0.078 V, where the electric charge amount Cpix of the liquid crystal capacitance 10 is 100 fF, and the electric charge amount Csd of the parasitic capacitance is 2 fF.
Since the voltage amplitude of liquid crystals (the maximum voltage applied to the liquid crystal capacitance 10) is around 5 V in general and one gray level will be 0.0195 V when 256 levels of gray should be displayed. Therefore, the variation as much as 0.078 V corresponds to four gray levels, which appears as a variation that is sufficiently recognizable with human eyes. Furthermore, in the case of a smaller voltage amplitude than the above, a visual variation will increase more, and therefore the influence thereof cannot be ignored.
Note here that although FIG. 14 exemplifies the configuration having two data lines DLs connected as one group to an output signal line D of the data line drive circuit 103, the number of the data lines in one group is not limited to two. As long as the pixels corresponding to a plurality of data lines DLs are driven successively in accordance with the scanning direction, a difference in the charged voltage of the liquid crystal capacitances 10 will increase between the first driven pixel and the last driven pixel in one horizontal period, thus causing a display unevenness in a stripe pattern.
In view of such a problem, another configuration has been proposed also, in which the connecting order of a plurality of data lines forming a group with an output signal line of a data line drive circuit is changed from one gate line to another and, even for the same gate line, the order is made different for each scanning operation (see Patent Document 2).
Patent Document 1: JP 1103 (1991)-74839 A
Patent Document 2: JP 2003-58119 A (FIG. 2 and FIG. 5)